Special Tracks

In addition to the general session, submissions are invited for the following tracks on reconfigurable computing applications and techniques

High Performance Reconfigurable Computing (Details)
co-Chairs
Paul Chow, University of Toronto, Canada
Ron Sass, UNC-Charlotte, USA

Reconfigurable Computing for Security and Cryptography (Details)
co-Chairs
Viktor Fischer, Université de Saint Etienne, France
Kris Gaj, George Mason University, USA

Reconfigurable Computing for DSP and Communications (Details)
co-Chairs
Christophe Bobda, University of Arkansas, USA
Jürgen Teich, University of Erlangen-Nuremberg, Germany

Multiprocessor Systems and Networks on Chip (Details)
co-Chairs
Michael Hübner, Karlsruhe University, Germany
Diana Göhringer, Fraunhofer-Institute, Germany

Reconfiguration techniques (Details)
co-Chairs
Joao Cardoso, University of Porto, Portugal
Marco D. Santambrogio, MIT, USA

Productivity Environments and High Level Languages (Details)
co-Chairs
Loïc Lagadec, University of Western Brittany, France

Controversy track: FPGAs Vs GPUs (Details)
co-Chairs
Ali Akoglu, University of Arizona, USA
Khaled Benkrid, University of Edinburgh, UK

Tracks Description

High Performance Reconfigurable Computing

Reconfigurable computing has been gaining attention in both the high-performance computing (HPC) and the high-performance embedded computing (HPEC) communities. The synergistic use of multiprocessing techniques and reconfigurable parallelism has shown orders of magnitude improvements in performance, power efficiency, and cost for many applications. Numerous emerging architectures (in-socket accelerators, tightly-coupled accelerators, homogeneous/heterogeneous Multi-processor Systems-on-Chips, embedded FPGAs, self-organizing computing substrates), techniques (dynamic/partial reconfiguration, run-time adaptability, hardware virtualization) and paradigms shifts (anti-machines, evolvable/bio-inspired systems) open new perspectives and contribute to widen the spectrum of potential benefits of reconfigurable hardware. However, widespread adoption of this technology is hampered by numerous difficulties in using the hardware and software. Both architectures and programming tools/methodologies lack the proper maturity and therefore pose severe limitations in term of usability for high-performance computing applications and high-performance embedded systems. The High-Performance Reconfigurable Computing (HPRC) track at ReConFig invites submissions from researchers and developers from this field as well as application scientists and HPC/HPEC communities attempting to use this technology to implement computationally intensive applications. Topics of interest include the following: • Systems and emerging architectures • Dynamic Hardware reconfiguration • Reconfigurable instruction set/VLIW processors and MPSoC architectures • Run-time environments • Libraries, standards, and interoperability • Performance modeling, prediction, and benchmarks • Scientific and engineering applications • Novel FPGA architectures for HPRC

Reconfigurable Computing for Security and Cryptography

Reconfigurable hardware offers unique opportunities for the design and implementation of secure applications in embedded and high-end computing platforms. High performance, carefully-controlled execution, and physical isolation are just a few of the advantages that hardware brings over software. At the same time, new challenges appear, such as the protection of intellectual property in a reconfigurable fabric, and the protection of soft-hardware against malicious tampering. This special track seeks the latest innovations in reconfigurable computing for security and cryptography. Topics of interest include the following: • Hardware Implementation of Novel Cryptographic Algorithms and Protocols • Reconfigurable Cryptographic Primitives • Special-Purpose Hardware for Cryptanalysis • Hardware Support for Trustworthy Software Execution • True and Pseudo Random Generators • Circuit Identification and Physical Unclonable Functions • Efficient Methods for Protection of Hardware IPs • FPGA Design Security • Fault Attacks and Side-channel Attacks • Hardware Tamper Resistance and Tamper Evidence • Hardware Trojan Detection and Resistance • Design Flows for Hardware-based Secure Systems • Performance Evaluation of Secure Reconfigurable Hardware

Reconfigurable Computing for DSP and Communications

The inherent parallelism in DSP algorithms and communication applications lends itself ideally to hardware implementation. Reconfigurable platforms have garnered wide use in the field, with communications companies still the primary users of programmable logic devices. With rapidly evolving standards and the constraints on time-to market, reconfigurable systems can provide an important edge in a fierce market. Manufacturers of programmable logic devices have recognised this, and continued to provide architectural features tailored to this field of application, thus enabling novel mappings of complex algorithms and systems. Recent developments in the communications field include a move to more adaptive systems. Cognitive radios are intelligent systems that adapt to environmental and infrastructure conditions in order to provide the best possible service and use of resources. Such systems are typically computationally intensive, and require significant reconfigurability, making them ideal candidates for implementation on reconfigurable platforms. Authors are invited to submit original contributions related to the following topics: • Platforms and tools for adaptive and cognitive radio systems • Novel reconfigurable architectures for communications and DSP Applications • Coarse-grain architectures for DSP • Low-power DSP architecture and implementation • Design tools for DSP and communications on reconfigurable platforms • Novel algorithms for DSP on reconfigurable platforms • Exploiting heterogenous resources on modern programmable logic devices for DSP application

Multiprocessor Systems and Networks on Chip

High-performance computing systems, for high-end servers as well or for embedded systems, a massive paradigm shift towards multicore architectures is taking place. Integrating multiple cores on a single chip leads to a significant performance improvement without increasing the clock frequency. Multicore architectures offer a better performance/Watt ratio than single core architectures with similar performance. Combining multicore and coprocessor technology promise extreme computing power for highly CPU-time-consuming applications in scientific computing as well as for special purpose applications in the embedded area. Especially FPGA-based accelerators not only offer the opportunity to speedup an application by implementing their compute-intensive kernels into hardware but also to adapt to the dynamical behavior of an application. The purpose of this workshop is to evaluate strategies for future system design in MPSoC architectures. Both aspects, hardware design and tool-integration into existing development tools will be discussed. Especially the novel trends in MPSoC combined with reconfigurable architectures are a main topic in this workshop. Furthermore, the on-chip intercommunication affects tremendously the performance of the complete device and is therefore a topic of high importance in this track. Authors are invited to submit original contributions related to the following topics: • Overview of actual and future Multiprocessor System on Chip (current architectures from industry and academics, future trends) • Tool Adaption / Extension for handling the complexity of actual and novel architectures • Reconfiguration Methods: Solution for well balanced load distribution on chip? • Industrial interests: Fields of application for MPSoC architectures • Multilevel parallelization and hybrid concepts on hierarchical systems • New optimized algorithms adapted to the specific architectures • Numerical methods compliant with the memory hierarchy • Adaptive schemes on heterogeneous architectures • Providing powerful programming models allowing programmers to express parallelism, data access, and synchronization • Supporting code partitioning between hardware and software • Developing tools for performance analysis and debugging • Virtualization technology to abstract applications from the underlying multicore architecture

Reconfiguration techniques

FPGAs (Field-Programmable Gate Arrays) are used to accelerate a wide spectrum of applications, in embedded as well as high-performance systems. Most current uses of FPGAs are static, where a design is programmed once and then used to execute the application. Partial and dynamic reconfiguration allow the reuse of hardware resources and possible hardware cost savings. Furthermore, by adopting dynamic reconfiguration, a system is able to accomplish virtualization, which can be used to allow portability. This track aims at providing a forum to discuss and present state-of-the-art industrial and academic experiences concerning reconfiguration techniques. Papers with contributions to the following topicsare particularly welcome: • The use of reconfiguration techniques to improve performance, save area, energy, etc. • Reconfiguration techniques to customize hardware resources (interconnections, functional units, buffers, multicore interconnect topologies, etc.) • Dynamic adaptation of architectures • Runtime mapping techniques allowed by dynamic reconfiguration • Hardware virtualization • Programming models and languages supporting reconfiguration techniques • Operating Systems supporting reconfiguration techniques • Design and compilation flows for dynamically reconfigurable devices • The use of dynamic reconfiguration techniques for prototyping circuits and systems • Reconfiguration techniques to deal with unreliability and to improve fault tolerance • Applications taking advantage of reconfiguration techniques

Productivity Environments and High Level Languages

High level synthesis aims at offering a simplified path from high-level languages like C/C++/Matlab - used to capture the design intent - to circuit, by opposition to low-level HDL languages or even manual RTL designs. It favors building software and hardware using a common model, making easier to co-design HW/SW systems and facilitating the co-validation. As a consequence, FPGA programming is made easier and the hardware designer's productivity increases, making affordable time-to-market constraints despite the growing complexity of systems. Recent developments in the automation of circuit generation have lead to a wide language coverage and robust compilation flows - reusing legacy tools such as gcc - that provide circuit of comparable if not better quality than manual designs. This special track seeks the latest innovations in high level languages support for reconfigurable computing, focusing on productivity and quality gain. Topics of interest include the following: • Advances in HLS tools • Productivity metrics and experience reports • Productivity gain using high level languages • Validation improvements using high level languages • Debugging-compliant HLS approaches • QoS improvements using high level languages • Hardware support for high level languages execution • Model driven engineering for reconfigurable computing • Novel approaches for fast prototyping-to-deployment shift • Late binding support in hardware • Formal methods for reconfigurable computing

Controversy Track: FPGAs Vs GPUs

Reconfigurable hardware in the form of FPGAs is facing increased competition from multi-core processors such as GPGPUs as the cost of purchase, programming, and maintenance of these is lower, or perceived to be lower. The low level programming model of FPGAs, in particular, is often seen as not only an impediment to further FPGA penetration of more mainstream computing but also as a threat to its existing market segments. This special track invites contributions from all point-of-views pertaining to this debate. In particular, we welcome papers presenting: • Comparative evaluations of FPGAs and multi-core processors in terms of: architecture and programming model, implementation speed, power efficiency, cost, and ease of maintenance. • Novel heterogeneous architectures and applications taking advantage of both FPGAs and multi-core processors. • Novel software tools for the unified design and programming of FPGAs and multi-core based architectures.