Reconfigurable computing has been gaining attention in both the high-performance computing (HPC) and the high-performance embedded computing (HPEC) communities. The synergistic use of multiprocessing techniques and reconfigurable parallelism has shown orders of magnitude improvements in performance, power efficiency, and cost for many applications. Numerous emerging architectures (homogeneous/heterogeneous Multi-processor Systems-on-Chips, embedded FPGAs, self-organizing computing substrates), techniques (dynamic/partial reconfiguration, run-time adaptability, hardware virtualization) and paradigms shifts (anti-machines, evolvable/bio-inspired systems) open new perspectives and contribute to widen the spectrum of potential benefits of reconfigurable hardware. However, widespread adoption of this technology is hampered by numerous difficulties in using the hardware and software. Both architectures and programming tools/methodologies lack the proper maturity and therefore pose severe limitations in term of usability for high-performance computing applications and high-performance embedded systems.

The High-Performance Reconfigurable Computing (HPRC) track at the 2008 International Conference on ReConFigurable Computing and FPGAs invites submissions from researchers and developers from this field as well as application scientists and HPC/HPEC communities attempting to use this technology to implement computationally intensive applications.

Topics
• Systems and emerging architectures for HPRC
• Dynamic Hardware reconfiguration in HPRC
• Reconfigurable instruction set/VLIW processors and MPSoC architectures
• High-level Languages, compilers, and tools
• Run-time environments for HPRC/HPEC
• HPRC libraries, standards, and interoperability
• Performance modeling, prediction, and benchmarks
• HPRC software-hardware co-design methodology, algorithms, and formal methods
• Scientific and engineering applications running on HPRC platforms

Reconfigurable computing has emerged as a flexible way to take advantage of hardware parallelism for massively distributed computing paradigms. Moreover, it has initiated a trend towards the design of computing devices based on large sets of elementary units. Fault tolerance, self-organization or adaptability are key concepts in this field, from evolvable hardware to spatial computing. Simultaneously, bioinspiration has taken advantage of increasing computing capabilities to build models, methods and algorithms that address particularly complex problems such as perception, self-organization or coordination (neural fields, models of social insects, pulsed networks, biocellular models, behavioral models, biomechanical models, etc.). This special track aims at gathering these two major current trends of the research about computing systems and models.

Papers that are related to both reconfigurable computing and bioinspiration are welcomed. We seek contributions about bioinspired approaches applied to reconfigurable systems and devices, as well as contributions about reconfigurable implementations of bioinspired models.

Topics include, but are not limited to:
• Bioinspired models and architectures for reconfigurable computing
• Bioinspired evolvable hardware
• Fault-tolerant computing systems and bioinspiration
• Self-organizing reconfigurable computing systems
• Bioinspired spatial computing
• Bioinspired computational models on reconfigurable hardware
• Bioinspired cognitive models on reconfigurable hardware
• Bioinspired control on reconfigurable hardware
• Bioinspired multi-agent models on reconfigurable hardware
• Neural networks on reconfigurable hardware

Security is a major drive in current research on the design of computing
platforms ranging from embedded to high-end systems. The trend is to move
the enforcement of certain security properties from the software layers into
the computing hardware. On one hand this opens the door to a wide range of
applications like hardware-based trusted computing or the efficient hardware
implementation of cryptography. On the other hand the reconfigurable
computing also creates new security issues like the protection of the
confidentiality of hardware IPs and softcores or the authentication of
system users.

The special track: “Reconfigurable Computing for Security and
Cryptography” will consider (but is not restricted to) the following topics:
• Hardware Implementation of Cryptographic Algorithms
• Efficient Methods for Protection of Hardware IPs
• Special Purpose Hardware for Cryptanalysis
• Hardware Support for Efficient Software Processing of Cryptography
• True and Pseudo Random Generator
• Cryptographic Processors and Co-Processors
• Hardware Tamper Evidence and Tamper Resistance
• Side Channel Attacks
• Prototyping of Novel Trusted Computing Primitives
• The Use of Reconfigurable Architectural Features for Trusted Computing

The inherent parallelism in DSP algorithms and communication applications lends itself ideally to hardware implementation. Reconfigurable platforms have garnered wide use in the field, with communications companies still the primary users of programmable logic devices. With rapidly evolving standards and the constraints on time-to market, reconfigurable systems can provide an important edge in a fierce market. Manufacturers of programmable logic devices have recognised this, and continued to provide architectural features tailored to this field of application, thus enabling novel mappings of complex algorithms and systems.

Recent developments in the communications field include a move to more adaptive systems. Cognitive radios are intelligent systems that adapt to environmental and infrastructure conditions in order to provide the best possible service and use of resources. Such systems are typically computationally intensive, and require significant reconfigurability, making them ideal candidates for implementation on reconfigurable platforms.

For the special track: "Reconfigurable Computing for DSP and Communications", authors are invited to submit original contributions related to the following topics:
• Platforms and tools for adaptive and cognitive radio systems
• Novel reconfigurable architectures for communications and DSP Applications
• Coarse-grain architectures for DSP
• Low-power DSP architecture and implementation
• Design tools for DSP and communications on reconfigurable platforms
• Novel algorithms for DSP on reconfigurable platforms
• Exploiting heterogenous resources on modern programmable logic devices for DSP application

45 nm has arrived and probably, within the 2 next years, the first chips with 32nm technology will be produced. The shrinking of silicon technologies feature sizes has allowed to design and to manufacture very complex systems-on-chip, with more than a billion of transistors. This ever growing complexity has brought together several issues such as design, verification, test and debug.

Beyond complexity, one of the most challenging issue relies on the fact that a chip will not necessarily behave as specified at design-time. One of the approach could be to adapt the system at run-time in order to compensate technological variability over space (inter and intra wafer variability) and time (evolution of the chip performances during its lifetime), but also to adapt the functionalities (reconfiguration, software updates, maintenance ) and the performances (DVFS, Dynamic Power Management, Temperature management). Adaptability could be handled by an external mechanism, but the evolving complexity of current systems requires that the chip should be capable to manage itself all of these mechanisms: this is what we call “Self adaptive Computing”.

Authors are invited to submit original contributions related to models, design, simulation and prototyping of “self-adaptive computing” systems.

Topics
• On-line monitoring and diagnostic methods
• Self-adaptive run-time reconfiguration
• Automatic on-line task (re-)mapping and task migration
• Models and architectures for self-adaptive systems
• Application and performances of Self-adaptive chips
• Low power self-adaptive systems using DVFS and DPM
• Temperature aware computing systems
• Variability aware computing systems