ReConFig's attendees and exhibitors are encouraged to bring their hardware/software for display at the ReConFig 2016 Demo Night that will be held on November 30th during the Conference Cocktail. There is no exhibition fee.
Demos should not necessarily be related to papers presented at the conference. If you have something interesting to show, we encourage you to participate.
Participation in the ReConFig 2016 Demo Night is restricted to registered attendees and exhibitors.
Software Toolflow for FPGA Bitstream Obfuscation
(1) University of Florida, USA
(2) - NXP Semiconductor, USA
Reconfigurable hardware, such as Field Programmable Gate Arrays (FPGAs), are being increasingly deployed in diverse application areas including automotive systems, critical infrastructures, and the emerging Internet of Things (IoT), to implement customized designs. However, securing FPGA-based designs against piracy, reverse engineering, and tampering is challenging, especially for systems that require remote upgrade. In many cases, existing solutions based on bitstream encryption may not provide sufficient protection against these attacks. In our paper (Karam et al., "Robust Bitstream Protection in FPGA-based Systems through Low-Overhead Obfuscation", ReConFig 2016), we presented a novel obfuscation approach for provably robust protection of FPGA bitstreams with low overhead. In this demonstration, we show how our custom software can integrate with a commercial FPGA toolflow for securing designs on existing hardware.
Rapid Design Assembly with GNURadio and RFNoC
Consolidated Logic Incorporated, USA
This demo highlights Consolidated Logic's Rapid Design Assembly technology that enables creation of custom Software Defined Radio designs in less than a minute using a library of precompiled blocks. This demonstration will highlight live assembly and deployment on a National Instruments USRP X310 device, featuring a Xilinx Kintex-7 FPGA.
Proof of Concept Demonstration of a Dynamic DFX Circular CORDIC
Oakland University, USA
Our demo consist on a continuation of our work presented at ReConFig ’16. In which by leveraging Dynamic Partial Reconfigurable (DPR) technology we implement a Dynamic Dual Fixed Point (DDFX) Circular CORDIC which is able to change its format at run time and thus improving accuracy and its dynamic range without any increase in logic usage. We will demo a self-reconfigurable embedded system that implements the DDFX Circular CORDIC on a Zybo (ARM/FPGA SoC) board to compute module and atan functions which later are verified in a graphical and quantitative way using MATLAB.
Presentation of an FPGA-based AMIDAR Processor Prototype
TU Darmstadt, Germany
AMIDAR stands for Adaptive Microinstruction Driven Architecture and is an adaptive class of processors. In this demo we present a prototype of an AMIDAR processor implemented on an FPGA. This processor executes Java Bytecode directly and contains a CGRA which is used as a general purpose hardware accelerator. The hardware accelerator can be reconfigured during runtime and thus creates a valuable foundation for research in the field of online synthesis of hardware accelerators.
Additionally, we will demonstrate the integrated on-chip debugger which allows the user to do software and hardware debugging simultaneously.
RePaBit: Automated Generation of Relocatable Partial Bitstreams for Xilinx Zynq FPGAs
Ruhr-University Bochum (RUB), Germany
Partial reconfiguration in FPGAs increases the flexibility of a system due to dynamic replacement of hardware modules. However, more memory is needed to store all partial bitstreams and the generation of all partial bitstreams for all possible regions on the FPGA is very time-consuming. In order to overcome these issues, bitstream relocation with the Xilinx Vivado tool flow is presented. In addition, the approach is automated by TCL scripts that extend Vivado to RePaBit. RePaBit is successfully evaluated on the Xilinx Zynq FPGA using 1D and 2D relocation of complex modules such as MicroBlaze processors. The results show a negligible overhead in terms of area and frequency while enabling more flexibility by partial bitstream relocation as well as faster design time.