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Demos and Projects Presentation

Demos and Projects Presentation

ReConFig's attendees and exhibitors are encouraged to bring their hardware/software for display at the ReConFig 2017 Demo Night that will be held on December 4 during the Conference Cocktail. There is no exhibition fee.

Attendees are also invited to present a poster to share your latest projects, research results, ideas or any other relevant material you would like to share with other attendees.

Demos and project presentations should not necessarily be related to papers presented at the conference. If you have something interesting to show, we encourage you to participate. 

 

Confirmed Demos and Project Presentation

 

DEMO: TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays

Ericles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, and J¨urgen Teich
Hardware/Software Co-Design, Department of Computer Science Friedrich-Alexander-Universit¨at Erlangen-N¨urnberg (FAU), Germany

Abstract
In the realm of heterogeneous Multi-Processor System-on-Chip (MPSoC) architectures, Coarse-Grained Reconfigurable Arrays (CGRAs) have emerged as a low-power and highly efficient solution for speeding up computations. However, designing such programmable hardware accelerators is a time consuming and non-trivial task. To ease the development process, we present the TCPA Editor: a Java-based graphical design environment for automatically generating Tightly Coupled Processor Arrays (TCPAs), a class of CGRAs that are highly parameterizable.
The tool is tailored for designing, simulating, prototyping, and testing TCPA architectures. These consist of a massively parallel array of tightly coupled VLIW processing elements. The core array is complemented by peripheral components, e.g., controllers and a reconfigurable memory architecture.
Based on the user’s design entries, the editor generates synthesizable VHDL codes that describe each instance of a TCPA component. The editor can also be used for assembly programming and graphical interconnect setup. These configurations are combined into one binary code, which is used to reconfigure the hardware at runtime.
Furthermore, the tool automatically generates synthesis parameters for today’s de facto standard for on-chip communication. Hence, TCPAs can be easily interfaced to memory-mapped devices and high-speed streaming data, which allows for burst transfers of unrestricted size. The editor presents itself as a very powerful and user-friendly design tool for improving productivity.
In the demonstration, we showcase our tool for the generation and system integration of TCPAs into heterogeneous MPSoC architectures. Finally, we present real-world case studies and synthesis results from different architectures prototyped in FPGA and ASIC technologies.

DEMO: NoCNet: An Omnet++ based Network-on-Chip performance evaluation tool.

Remberto Sandoval-Arechiga, Salvador Ibarra-Degado and Jorge Flores-Troncoso
Zacatecas Autonomous University, Mexico

Network-on-Chip’s performance evaluation plays an important role in the design process. Functionality problems and bottlenecks can be identified and corrected in early stages in the design. However, performance evaluation tools can be broadly categorized in two: general tools that do not capture all the required details for Networks-on-Chip and architecture specific tools that only focuses in some precise features. NoCNet is a performance evaluation framework based in Omnet++ that aims to overcome these problems. NoCNet uses C++ classes to describe hardware and software in a very versatile manner, which brings the capability of create complex features, topologies and simulation scenarios. The use of NoCNet is exemplified by means of a Software-Defined Network-on-Chip scenario, where the performance evaluation and debugging of the NoC can be assisted by the NoCNet framework and the different tools provided by Omnet++.

DEMO: EMA as a mean to find spatial and time SCA leakage sources

Ievgen Kabin, Elisabeth Vogel, Zoya Dyka and Peter Langendoerfer
IHP, Frankfurt (Oder), Germany

We present our software for an automated Electromagnetic Analysis (EMA) attack against Elliptic Curve Cryptography (ECC) designs. The attacked design used in this demo is an EC point multiplication kP that is the main ECC operation. The kP operation is implemented for the NIST EC B-233 and is resistant against SPA. We ported an IHP kP design [1] implemented in VHDL to a Xilinx Spartan-6 FPGA. We measured EM traces over the chip using a horizontal EM probe and captured them using a LeCroy Waverunner 610Zi oscilloscope.
Our software processes the captured traces automatically. Different compression methods of the measured traces are implemented and can be compared. Statistical analysis of each trace is performed using the difference of the mean as described in [2], i.e. a horizontal differential EMA attack is performed against each single trace. Using our software we revealed the scalar k. Thus, it can be used in attacks against ECDSA. We discovered not only a spatial but also a time based leakage sources that can be exploited in Side Channel Analysis attack. The information about spatial and time based SCA leakage is very helpful for a redesign.
In the demo we show how our tool can be used to analyse traces as described above. We will use prerecorded traces and focus on the evaluation, which comes with a nice GUI that helps to understand the analysis results and to get the idea of the tool support. The following figures show sample snapshots of the GUI we present.

[1] IHP - Innovations for High Performance Microelectronics, https://www.ihp-microelectronics.com.
[2] I. Kabin, Z. Dyka, D. Kreiser and P. Langendoerfer, Horizontal Address-Bit DPA against Montgomery kP Implementation, Proc. of ReConFig-2017, Dec 4-6, 2017, Cancun, Mexico.

Project Presentation: The EXTRA open reconfigurable platform for HPC

Dirk Stroobandt, Ghent University, Belgium
Dionisios Pnevmatikatos, Telecommunication Systems Institute, Greece
Gabriel Figueiredo, Imperial College London, UK
Marco Santambrogio, Politecnico di Milano, Italy
Ana Verbanescu, University of Amsterdam, The Netherlands
Michael Hübner, Ruhr Universität Bochum, Germany
Tobias Becker, Maxeler Technologies Ltd., UK
Andreas Brokalakis, Synelixis Solutions Ltd., Greece
Alex Thom, University of Cambridge, UK

Project Presentation: Tool Flow for Automatic Generation of Architectures and Test-Cases to Enable the Evaluation of CGRAs in the Context of HPC Applications

André Werner, Florian Fricke und Michael Hübner
Ruhr University Bochum, Germany

Project Presentation: Sketching Streaming-Graphs using FPGAs.

Usman Tariq, Fahad Saeed
Department of Electrical & Computer Engineering and Department of Computer Science, Western Michigan University, USA

Project Presentation: CERBERO - Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments

Francesca Palumbo
Università degli Studi di Sassari, Italy

Project Presentation: TULIPP: Towards Ubiquitous Low-power Image Processing Platforms

Diana Goehringer
TU Dresden, Germany

Project Presentation: NODAL: an Open Distributed Autotuning Library

Pedro Bruel and Alfredo Goldman
University of São Paulo, Brazil

Project Presentation: A Reconfigurable Baseband Radio for Satellite Communications

Salvador Ibarra-Delgado, Remberto Sandoval Arechiga, Laura Garcia-Luciano, Jorge Flores-Troncoso
Zacatecas Autonomous University, Mexico