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Workshops

Registration information for workshops will be posted here shortly.

 

FPGA-based Accelerated Cloud Computing with SDAccel - Xilinx Workshop

Workshop
FPGA-based Accelerated Cloud Computing with SDAccel
Parimal Patel
Xilinx

Sunday December 2th

Register here

The increasing computational requirements of next-generation Cloud and High-Performance Computing (HPC) applications are pushing the adoption of accelerated computing based on heterogeneous architectures into mainstream, as traditional CPU technology is unable to keep pace. Xilinx FPGAs are now available, in two different sizes that include up to eight Virtex® UltraScale+ VU9P, on the Amazon Elastic Compute Cloud (EC2) F1 instances, which are designed to accelerate data center workloads, including machine learning inference, data analytics, video processing, and genomics. Furthermore, Amazon Web Services offers the SDAccel™ Development Environment for cloud acceleration, enabling the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto the heterogeneous CPU-FPGA system.
SDAccel completely automates the step of the hardware design flow, offering an easy to use environment for FPGA application design. It offers the possibility to specify a compute kernel using C and C++ for higher-level algorithmic implementation, or using hardware description languages for RTL designs, while using OpenCL APIs to control run-time behavior. Attendees will use their laptops to connect to the EC2 F1 instances.

Proposed Workshop Agenda (AWS)
  • Class Intro (9:00 AM – 9:15 AM)
  • Introduction to AWS EC2 F1 (9:15 AM – 10:00 AM)
  • Lab 1: Connecting to AWS EC2 F1 lab (15 mins)
  • Morning break (10:15 AM – 10:30 AM)
  • SDAccel Tools Overview (10:30 AM – 10:45 AM)
  • Lab 2: MakeFile Flow lab (10:45 AM – 11:30 AM)
  • SDAccel Flow (11:30 AM – Noon)
  • Lunch
  • SDAccel Flow (Cont) (1:00 PM – 1:30 PM)
  • Lab 3: GUI Flow lab (1:30 PM – 2:15 PM)
  • Optimization Techniques (2:15 PM – 3:00 PM)
  • Afternoon break (3:00 PM – 3:15 PM)
  • Lab 4: Optimization lab (3:15 PM – 4:00 PM)
  • RTL Kernel Wizard (4:00 PM – 4:30 PM)
  • Lab 5: RTL Kernel Creation lab (4:30 PM – 5:00 PM)
  • Debugging Techniques / Machine Learning (5:00 – 5:30 PM)
  • Lab 6: Debugging/Machine Learning on AWS EC2 F1 lab (5:30 PM – 6:00 PM)