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Tracks

Special Tracks

In addition to the general sessions, submissions are invited for the following tracks on reconfigurable computing applications and techniques.

High Performance Computing Systems and Applications

Co-chairs

Jason Bakos, University of South Carolina, USA
Andrew Schmidt, ISI/USC, USA

Description 

Reconfigurable computing has been gaining attention in both the high-performance computing (HPC) and the high-performance embedded computing (HPEC) communities. The synergistic use of multiprocessing techniques and reconfigurable parallelism has shown orders of magnitude improvements in performance, power efficiency, and cost for many applications. Numerous emerging architectures (in-socket accelerators, tightly-coupled accelerators, homogeneous/heterogeneous Multi-processor Systems-on-Chips, embedded FPGAs, self-organizing computing substrates), techniques (dynamic/partial reconfiguration, run-time adaptability, hardware virtualization) and paradigms shifts (anti-machines, evolvable/bio-inspired systems) open new perspectives and contribute to widen the spectrum of potential benefits of reconfigurable hardware. However, widespread adoption of this technology is hampered by numerous difficulties in using the hardware and software. Both architectures and programming tools/methodologies lack the proper maturity and therefore pose severe limitations in term of usability for high-performance computing applications and high-performance embedded systems.
 
The High-Performance Reconfigurable Computing (HPRC) track at ReConFig invites submissions from researchers and developers from this field as well as application scientists and HPC/HPEC communities attempting to use this technology to implement computationally intensive applications.

Topics

  • Systems and emerging architectures
  • Dynamic Hardware reconfiguration
  • Reconfigurable instruction set/VLIW processors and MPSoC architectures
  • Run-time environments
  • Libraries, standards, and interoperability
  • Performance modeling, prediction, and benchmarks
  • Scientific and engineering applications
  • Novel FPGA architectures for HPRC

Cloud and Data Center Systems and Applications

Co-chairs

Tobias Kenter, Paderborn University, Germany
Paul Chow, University of Toronto, Canada

Description 

In 2014 Microsoft described the use of FPGAs to accelerate their Bing search engine. This was the first large-scale experiment proving that FPGAs can provide significant benefits in the data center. Then Amazon introduced the EC2 F1 instances in 2017, which has attracted significant interest from application developers. This was the point when FPGAs could be rented by anyone accessing the cloud, either as a physical device or through a service available in the AWS Marketplace. It has taken a long time for FPGAs to achieve this level of legitimacy as reconfigurable computing devices and much of that can be attributed to the fundamental difficulties of programming FPGAs. We all know about those issues, and now that FPGAs have arrived in the cloud, there are even bigger challenges. How do we manage and use FPGAs in a cloud environment? What architectural features will make FPGAs better citizens in the cloud? What applications can leverage FPGAs in the cloud? The Cloud and Data Center Systems and Applications track has a focus on presenting research that addresses any aspects related to the use of FPGAs in large-scale systems related to the cloud and data centers.

Topics

The following list is a guideline for relevant topics and should not be considered as an exclusive list. However, it is required that the topic has a connection to cloud and data centers.

- Architectures for Data Center FPGAs
- FPGA virtualization - from abstractions that hide the physical FPGA to multi-tenant sharing of a physical FPGA
- Security - including issues related to sharing physical devices, network access, denial of service, physical attacks, bit stream validation and security
- Power management and measurement
- Low power systems in the data center
- Performance measurement, analysis of work and data distribution
- Management of FPGA resources, such as FPGAs in OpenStack
- Resilience to failures
- Application deployment - how applications are loaded into the FPGAs
- Runtimes and scheduling
- Data consistency and availability
- Network file systems and stores
- Using FPGAs in Virtual machines and containers
- Debugging and simulation
- Programming models for heterogeneous multi-FPGA + multi-CPU systems
- Enabling FPGAs in big data platforms
- Applications in a cloud and data center environment

Multiprocessor and Heterogeneous Architectures (FPGAs, GPUs, and APUs)

Co-chairs

Diana Goehringer, TU Dresden, Germany
Thilo Piontheck, Universitat Magdeburg, Germany

Description

High-performance computing systems, for high-end servers as well or for embedded systems, a massive paradigm shift towards multicore architectures is taking place. Integrating multiple cores on a single chip leads to a significant performance improvement without increasing the clock frequency. Multicore architectures offer a better performance/Watt ratio than single core architectures with similar performance. Combining multicore and coprocessor technology promise extreme computing power for highly CPU-time-consuming applications in scientific computing as well as for special purpose applications in the embedded area. Especially FPGA-based accelerators not only offer the opportunity to speedup an application by implementing their compute-intensive kernels into hardware but also to adapt to the dynamical behavior of an application. The purpose of this workshop is to evaluate strategies for future system design in MPSoC architectures. Both aspects, hardware design and tool-integration into existing development tools will be discussed. Especially the novel trends in MPSoC combined with reconfigurable architectures are a main topic in this workshop. Furthermore, the on-chip intercommunication affects tremendously the performance of the complete device and is therefore a topic of high importance in this track.

Authors are invited to submit original contributions related to the following topics:
  • Overview of actual and future Multiprocessor System on Chip (current architectures from industry and academics, future trends)
  • Tool Adaption / Extension for handling the complexity of actual and novel architectures
  • Reconfiguration Methods: Solution for well balanced load distribution on chip?
  • Industrial interests: Fields of application for MPSoC architectures
  • Multilevel parallelization and hybrid concepts on hierarchical systems
  • New optimized algorithms adapted to the specific architectures
  • Numerical methods compliant with the memory hierarchy
  • Adaptive schemes on heterogeneous architectures
  • Providing powerful programming models allowing programmers to express parallelism, data access, and synchronization
  • Supporting code partitioning between hardware and software
  • Developing tools for performance analysis and debugging
  • Virtualization technology to abstract applications from the underlying multicore architecture

Productivity Environments and High Level Languages

Co-chairs

Eduardo de la Torre, Technical University of Madrid, Spain
Michael Huebner, Ruhr University Bochum, German

Description 

Design productivity remains a significant impediment to the more widespread adoption of reconfigurable computing for many high performance computing application areas. Unlike software development environments which are characterized by high-level, rapid, and interactive development/debug flows, FPGA-based reconfigurable computing design remains a mostly batch-oriented hardware design activity relying on HDL's, RTL synthesis, and logic analyzers. However, design productivity can be enhanced in a number of ways, including: the use of high level languages and High Level Synthesis (HLS), the use of rapid prototyping CAD tool flows to reduce synthesis, place, and route times (possibly allowing for a tradeoff of tool runtime against quality of result), the use of formal methods, the use of advanced verification methodologies such as hardware-in-the-loop debug and verification, the use of emulation platforms, etc.
 
This special track seeks the latest innovations in productivity tools and approaches for reconfigurable computing, focusing on productivity and quality gain.

Topics

  • Productivity metrics and experience reports
  • Advances in HLS tools
  • Productivity gain using high level languages
  • Rapid prototyping approaches
  • Formal methods for reconfigurable computing
  • Validation improvements using high level languages
  • Rapid debugging environments
  • Late binding support in hardware
  • Model driven engineering for reconfigurable computing
  • Debugging-compliant HLS approaches
  • QoS improvements using high level languages
  • Hardware support for high level languages execution
  • Novel approaches for fast prototyping-to-deployment shift

Real Time Image and Signal Processing

Co-chairs

Sonia Lopez-Alarcon, Rochester Institute of Technology, USA
Alfonso Avila, Tecnologico de Monterery, Mexico

Description

Modern FPGAs devices offer DSP-optimized capabilities that deliver the right balance of high-performance logic, serial connectivity and signal processing capabilities. This track welcomes submissions on all aspects of reconfigurable computing and FPGA devices applied to digital signal processing applications.

Topics

Topics include, but are not limited to:
  • Novel reconfigurable architectures for signal processing applications
  • Coarse-grain architectures for signal processing
  • Low-power signal processing architecture and implementation
  • Design tools for signal processing on reconfigurable platforms
  • Novel algorithms for signal processing reconfigurable platforms
  • Exploiting heterogenous resources on modern programmable logic devices for signal processing applications

Security, Cryptography, Fault Tolerance, and High Assurance

Co-chairs

Nele Mentens, KU Leuven, Belgium

Description 

Reconfigurable hardware offers unique opportunities for the design and implementation of secure applications in embedded and high-end computing platforms. High performance, carefully-controlled execution, and physical isolation are just a few of the advantages that hardware brings over software. At the same time, new challenges appear, such as the protection of intellectual property in a reconfigurable fabric, and the protection of soft-hardware against malicious tampering. This special track seeks the latest innovations in reconfigurable computing for security and cryptography. 

Topics

  • Hardware Implementation of Novel Cryptographic Algorithms and Protocols
  • Reconfigurable Cryptographic Primitives
  • Special-Purpose Hardware for Cryptanalysis
  • Hardware Support for Trustworthy Software Execution
  • True and Pseudo Random Generators
  • Circuit Identification and Physical Unclonable Functions
  • Efficient Methods for Protection of Hardware IPs
  • FPGA Design Security
  • Fault Attacks and Side-channel Attacks
  • Hardware Tamper Resistance and Tamper Evidence
  • Hardware Trojan Detection and Resistance
  • Design Flows for Hardware-based Secure Systems
  • Performance Evaluation of Secure Reconfigurable Hardware

Machine Learning

Co-chairs

Gabriel Wiesz, Microsoft, USA
Tinoosh Mohsenin, University of Maryland Baltimore County, USA

Description

TBA