Keynote Speakers

Andrew Putnam, Microsoft Research, USA


FPGAs at HyperScale -- The Past, Present, and Future of the Reconfigurable Cloud


Microsoft first deployed FPGAs at hyperscale in 2015. Since then, Microsoft’s cloud has continued to grow exponentially, providing developers with a greater capacity of reconfigurable computing logic than has ever been deployed. Accelerated networking (AccelNet), deep neural network inference (BrainWave), and web search (Catapult) are among the most prominent applications deployed in production at hyperscale today.
We have learned a number of lessons in the first few years of deployment – what to do, what not to do, how to structure development teams, and the kinds of problems that only occur at hyperscale. In this talk, I’ll discuss what we’re doing with the current fleet of FPGAs, some of the lessons we’ve learned along the way, what those lessons mean for the future of reconfigurable computing in the Cloud, and what the future holds for reconfigurable computing in the Cloud and Edge.

Dr. Andrew Putnam is Principal Hardware Development Engineer in Microsoft Research and Azure Networking. He is the co-founder of the Microsoft Catapult project, which was the first to put Field Programmable Gate Arrays (FPGAs) into production hyperscale data centers, doubling the capacity of each server for web search, and creating the fastest network in the cloud. He received a dual B.A/B.S. in Physics, Computer Science, and Electrical Engineering from the University of San Diego in 2003, and an M.S. and Ph.D. in Computer Science and Engineering from the University of Washington in 2006 and 2009 respectively.

Erich Devendorf, Air Force Research Laboratory, USA


Just in Time Mission Composition: Tipping the Assurance Balance in Cyberspace


Cyber attacks are founded on mastery of two of the principles of conflict: Initiative and Economy of Force. Threat actors enjoy nearly unlimited time to plan, prepare and execute attacks. These attacks are executed at the time and place of the attacker's choosing. With little effort, an attack against a single platform can instead strike an arbitrary number of additional targets.
We seek to tip the balance from offense to assurance through just-in-time mission composition in one-time-use hardware. Paramount to this shift in paradigm is the transition from “systems” which currently focus on reuse and homogeneity, to heterogeneous, one-time “instantiations” of missions. The latter coincides with the shift of focus to assurance via information assurance rather than cyber security or system assurance.
Instead of a baseline system which we define by its properties, we focus on an instantiation of a mission. This instantiation takes form via a one-time-use hardware design that is created by mission parameters and transformed into its carnal form. The shift away from systems to mission instantiations means that we no longer possess homogenous systems, but rather randomized, heterogeneous entities constructed to perform the mission.
This talk provides context for the balance of power between offense and defense in cyberspace. It argues that the foundation of that power is based on initiative and economy of force and posits that defense intrinsically possesses these same advantages. It then examines FPGA's as a means to support mission assurance and advocates a paradigm shift away from general purpose computing to mission appliances without shared vulnerability.

Dr. Erich Devendorf is the Director of the Advanced Course in Engineering and an AFRL Early Career Award recipient. As a Computer Engineer at the Air Force Research Laboratory Information Directorate, Dr. Devendorf addresses challenges at the boundaries between Air, Space and Cyberspace. His R&D efforts have a mission focus, with an emphasis on transforming the composition of the cyber domain. Dr. Devendorf advocates a fundamental shift away from homogenous systems to heterogeneous entities designed to complete the mission. He has participated in weapons systems cyber vulnerability assessments and is a member of the AFOTEC Cyber Blue Book™ team.
Dr. Devendorf is working on the development of theater scale cyber wargames to explore the impact and limitations of cyber as a tool of national policy. These wargames support his interest in the doctrine and strategy required to seize the burgeoning cyber revolution in military affairs. He is an advocate for experimentation with novel education and training programs to develop cyber warriors. He has participated in military exercises in support of the cyber aggressors. This experience has shaped his design and execution of holistic military training that includes exercises that require cross-domain effects executed against an asymmetric adversary. These exercises interweave the kinetic and cyber domain to provide immersive training and cross domain fires in support of operational objectives.

Hugo A. Andrade, Director, Xilinx University Program, USA


Adaptable Intelligent Computing from Edge to Cloud

Recent technical challenges have forced the industry to explore options beyond the homogeneous “one size fits all” CPU scalar processing solution. Vector processing (DSP, GPU) solves some problems but runs into traditional scaling challenges due to inefficient memory bandwidth usage. Traditional FPGA solutions provide programmable memory hierarchy, but the traditional hardware flow has been a barrier to adoption. The solution is to combine all three elements with a new tool flow that offers a variety of different abstractions - from framework- to C- to RTL-level coding. Such an adaptive compute acceleration platform (ACAP) allows users to customize their own domain specific architecture (DSA) from these three programmable elements.
In this talk, we will review the motivation for this new ACAP device category, overview its broad applicability from cloud to edge domains, and present details about the first ACAP, its architecture and programming environment. We will also provide updates on some of our open source initiatives to enhance developer productivity.

Hugo A. Andrade is Director of the Xilinx University Program (XUP), currently focused on empowering academic teaching, research and entrepreneurship for adaptable compute acceleration in cloud and on-premise, and tools to improve developer productivity. Before joining Xilinx in San Jose, CA, he was most recently Principal Product Manager, Advanced Software Technologies, at National Instruments in Berkeley, where he worked on tools for system level design for heterogeneous platforms. He has been a visiting industrial fellow at the University of California, Berkeley, and was founding manager and technical lead of the NI Berkeley LabVIEW R&D site. Hugo has authored or co-authored 65 patents, over 25 academic research articles, as well a number of research prototypes, in the areas of instrumentation software, hardware/software interfacing, reconfigurable computing, graphical programming, models of computation, and system level design. He earned BS degrees in ECE and CS, and an MS degree in ECE from the University of Texas at Austin.