Program

Technical Program

  Monday Dec 9th Tuesday Dec 10th Wednesday Dec 11th
8:00-17:00 Registration Registration Registration
8:45-9:00 Welcome    
9:00-10:10 

Keynote #1: The future of Reconfigurable Computing: More than Meets the Eye.  Jose Alvarez, Intel

Session Chair: David Andrews

Keynote #2: Global-Scale FPGA-Accelerated Deep Learning Inference with Microsoft's Project Brainwave, Gabriel Weisz, Microsoft

Session Chair: Rene Cumplido

Keynote #3:  Security Challenges with Modern Reconfigurable Devices, Tim Guneysu, Ruhr-University Bochum, Germany

Session Chair: Marco Platzner

 

10:10-10:30 Short Break & Group Photo Short Break Short Break
 

Session M1:  HPCS

Session Chair: Ron DeMara

Session T1: AI and Machine Learning

Session Chair: Ron Sass

Session W1:Cryptography/Security

Session Chair: Nele Mentens

10:30-11:00  Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Norbert Wehn and Andreas Dengel. "iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction" Ali Mirzaeian,  Houman Homayoun and Avesta Sasan, " TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs" Sunwoong Kim, Keewoo Lee, Wonhee Cho, Jung Hee Cheon and Rob Rutenbar,  " FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption"
11:00-11:30 Shanyuan Gao and Sen Ma, " The Impact of Adopting Computational Storage in Heterogeneous Computing Systems" Tatsuya Kaneko, Hiroshi Momose and Tetsuya Asai, " An FPGA Accelerator for Embedded Microcontrollers implementing a Ternarized Backpropagation Algorithm" Joseph Gravellier, Jean-Max Dutertre, Yannick Teglia and Philippe Loubet Moundi, " High-Speed Ring-Oscillator based Sensors for Remote Side-Channel Attacks on FPGAs"
11:30-12:00 Andrew Wilson and Michael Writhlin, "Reconfigurable Real-Time Video Pipelines on SRAM-based FPGAs" Sina Boroumand and Philip Brisk,  "Approximate Adder Tree Synthesis for FPGAs" Tolga Yalcin and Elif Bilge Kavun, " Almost-Zero Logic Implementation of Troika Hash Function on Reconfigurable Devices"
12:00-12:10 Samah Rahamneh and Lina Sawalha,"Efficient OpenCL Accelerators for Canny Edge Detection Algorithm on a CPU-FPGA Platform" Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato and Hiroki Nakahara," FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System" Arkan Alkamil and Darshika G.  Perera,  "Efficient FPGA-Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms"
12:10-12:20 Andrei Hagiescu, Martin Langhammer, Bogdan Pasca, Philip Colangelo, Jason Thong and Niayesh Ilkhani, " BFLOAT MLP Training Accelerator for FPGAs" Abdelrahman Elkanishy, Derrick Rivera, Paul Furth, Abdel-Hameed A. Badawy, Youssef Aly and Christopher P. Michael, " FPGA-Accelerated Decision Tree Classifier for Real-Time Supervision of Bluetooth SoC" Abubakr Abdulgadir, William Diehl and Jens-Peter Kaps, " An Open-Source Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers"
12:20-13:30 Lunch
 

Session M2: Overlays, CGRAs,HLS

Session Chair: Shanyuan Gao

Session T2:Image and Pixel Processing

Session Chair: Darshika Perera

Session W2:Mixed Signal and Fault Injection

Session Chair: Dirk Stroobandt

13:30-14:00 David Wilson and Greg Stitt, " Seiba: An FPGA Overlay-Based Approach to Rapid Application Development" Ismael Antonio Dávila-Rodríguez, Marco Aurelio Nuño-Maganda, Yahir Hernández-Mier and Said Polanco-Martagón, " Decision-Tree Based Pixel Classification for Real-time Citrus Segmentation on FPGA" Adrian Tatulian, Soheil Salehi and Ronald F.  DeMara, "Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing"
14:00-14:30 Caleb Donovick, Makai Mann, Clark Barrett and Pat Hanrahan, " Agile SMT-Based Mapping for CGRAs with Restricted Routing Networks" Atiyehsadat Panahi, Keaten Stokke and David Andrews, " A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs" Burak Unal, Md Sahil Hassan, Joshua Mack, Nirmal Kumbhare and Ali Akoglu. "Design of High Throughput FPGA Based Testbed for Accelerating Error Characterization of LDPC Codes"
14:30-15:00 Guilherme Korol, Michael Jordan, Raul Silveira Silva, Monica Magalhães Pereira, Marcelo Brandalero, Mateus Beck Rutzig and Antonio Carlos Schneider Beck, " A Runtime Power-Aware Phase Predictor for CGRAs" Corbin Thurlow, Hayden Rowberry and Mike Wirthlin, " TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs" Closing Remarks
15:00-15:10 Wesley Stirk and Jeffrey Goeders, " Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis" Tomáš Beneš, Matěj Bartík and Pavel Kubalík, " High Throughput and Low Latency LZ4 Compressor on FPGA"  
15:10-15:20  Kevin Millar, Marcin Łukowiak and Stanislaw Radziszowski,  "Design of a Flexible Schonhage-Strassen FFT Polynomial Multiplier with High-Level Synthesis to Accelerate HE in the Cloud" Siavash Rezaei, Eli Bozorgzadeh and Kanghee Kim. "UltraShare: FPGA-based Dynamic Accelerator Sharing and Allocation"  
15:20-16:00 Coffee Break Coffee Break: Poster Session  
 

Session M3: Systems

Session Chair: Ali Akoglu

Session T3: Resource Optimizations

Session Chair: Eli Bozorgzadeh

 
16:00-16:30 Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann and Jürgen Teich. " Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs" Patrick Sittel, Nicolai Fiege, Martin Kumm and Peter Zipf, " Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling"  
16:30-17:00 Carsten Heinz, Yannick Lavan, Jaco Hofmann and Andreas Koch, " A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors" Nils Voss, Stephen Girdlestone, Tobias Becker, Oskar Mencer, Wayne Luk and Georgi Gaydadjiev."Low Area Overhead Custom Double Buffering for FFT"  
17:00-17:10 Habib Khan, Gökhan Akgün, Ariel Podlubne, Felix Wegener, Amir Moradi and Diana Göhringer, "Cycle-accurate Debugging of Multi-clock Reconfigurable Systems" Ievgen Kabin, Alejandro Sosa, Zoya Dyka, Dan Klann and Peter Langendoerfer, " On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack"  
17:10-17:20 Ariel Podlubne and Diana Goehringer, " FPGA-ROS: Methodology to Augment the Robot Operating System with FPGA Designs" Regina Marcela Ivo and Daniel M. Muñoz. "RTRLib: A High-Level Modeling Tool for the Implementation of Dynamically Partial Reconfigurable System-on-Chips"  
       
19:00-21:00 Welcome Cocktail & Demo Night 20:00-22:30 Banquet  



Poster Session

Tuesday Dec 10th, 3:20-4:00 

Abhi D.R., Ron Sass and Andrew Schmidt. "Volcan: System Integration of HLS and HMC on FPGAs"

Muhamamd Mudussir Ayub, Habibullah Ahmadzay, Josef Eckmueller and Franz Kreupl.  "Electronic System-Level Power and Performance Analysis for Multi-Processor-System-on-Chip"

Tomohiro Kida, Yuichi Kawamata, Yuichiro Shibata and Kentaro Sano. "A High Level Synthesis Approach for Application Specific DMA Controllers"

Elif Bilge Kavun, Nele Mentens, Jo Vliegen and Tolga Yalcin. "Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs"

Michal Andrzejczak, Farnoud Farahmand and Kris Gaj. "Full-hardware implementation of the Post-Quantum Public Key Cryptography Scheme Round5"

Cristian Urlea, Wim Vanderbauwhede and Syed Waqar Nabi. "Efficient FPGA Cost-Performance Space Exploration Using Type-driven Program Transformations"

Beck Strohmer, Anders Bøgild, Anders Stengaard Sørensen and Leon Bonde Larsen. "ROS-Enabled Modular Hardware Framework for Experimental Robotics"

 

Oral presentations Instructions

Please arrive at your lecture room in time, it is recommended to arrive at least 15 minutes before the start of the session in which you are presenting. Bring your presentation file in a USB memory stick.
Note that the AC voltage in Mexico is 120V (60Hz), American type plug (American standard NEMA 5-15).
The duration of each presentation slot is:
* 30 minutes for full papers, including time for the actual presentation (25 min) and questions from the audience (5 min).
* 10 minutes for short papers (No questions from the audience).
Please practice your presentation in advance; the session chair may cut the presentation short whenever necessary.
Do not put an excessive amount of text on your slides. Generally, all text should be 18 points or larger. Use clearly contrasting colors. Use graphics and colors to illustrate your presentation.

Equipment used for presentations

PC with Microsoft Windows with PowerPoint and Acrobat Reader.
Video projector (HDMI and VGA ports available)
Microphone
Laser pointer

Poster presentations Instructions

All posters must be printed in advance. No support will be given for printing at the conference venue.
There is not a strict limit on poster dimensions, although we recommend not to exceed 100cm x 150cm (width x height). Posters will be attached to the boards by conference staff. Please leave your poster with the staff at the registration desk at least one hour before the beginning of your poster session. The presenting author must be at the poster during the poster session.

Include the title of the paper on the top of the poster, in capital letters. Insert author names and affiliations below the title. The flow of the poster should be from the top left to the bottom right. Multiple columns can also be used. Using graphics and colors to illustrate your presentation is highly recommended.

© 2019 INAOE

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